Two-dimensional (2D) (planar) transistors can be improved by incorporating a ferroelectric film in the gate dielectric stack and the combination is known as a Negative Capacitance Transistor. The improvements include subthreshold swing that is smaller than 60 mV/decade and the extremely important lower operating voltage. These improvement leads to lower operating power, which is roughly proportional to the voltage squared. However, through years of study, the inventor of the present application discovered that the 2D negative capacitance transistors require costly and unusual substrate structures (nm thin P-on-P+ epitaxial layer or nm thin buried oxide) to achieve satisfactory performance through capacitance matching (between ferroelectric capacitance and MOS capacitance) and suppression of short channel effects. In addition, it is beneficial for many applications to minimize the sub threshold voltage swing of a transistor.